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| FEATURES n n n LTC6601-2 Low Power, Low Distortion, 5MHz to 27MHz, Pin Configurable Filter/ADC Driver DESCRIPTION The LTC(R)6601-2 is a low power, low distortion, very easy-to-use fully differential 2nd order active broadband RC filter and driver. On-chip resistors, capacitors, and amplifier bandwidth are trimmed to provide consistent and repeatable filter characteristics. The filter characteristics are pin-strap configurable. Cutoff frequencies range from 5MHz to 27MHz. Gain is pin-strap programmable between -17dB and +17dB. A three-state BIAS pin is provided to adjust amplifier power consumption. Select between low power (50% power reduction), high performance and standby modes with the BIAS pin. The LTC6601 family comes in two options which trade off distortion and noise. The LTC6601-2 offers the lowest distortion at high frequencies. The LTC6601-1 is configured for lowest noise. Both are available in pin-compatible packages. The LTC6601-2 is available in a compact 4mm x 4mm 20-pin leadless QFN package. L, LT, LTC and LTM are registered trademarks of Linear Technology Corporation. All other trademarks are the property of their respective owners. Protected by U.S. Patents including 6271719. n n n n n n n Pin Configurable Gain and Filter Response Up to 27MHz Low Power: 16mA at 3V Low Distortion (2VP-P) 1MHz: -96dBc 2nd, -112dBc 3rd 10MHz: -65dBc 2nd, -78dBc 3rd Few External Components Required Resistors Trimmed to 0.5% Accuracy Typical Capacitors Trimmed to 0.5% Accuracy Typical Adjustable Output Common Mode Voltage Rail-to-Rail Output Swing Power Configurability and Low Power Shutdown Tiny 0.75mm 20-Lead (4mm x 4mm) QFN Package APPLICATIONS n n n n n n Differential A/D Converter Driver Antialiasing/Reconstruction Filter Single-Ended to Differential Conversion/Amplification Low Voltage, Low Noise, Differential Signal Processing Common Mode Voltage Translation Portable Instrumentation TYPICAL APPLICATION Distortion Comparison Between LTC6601-1 and LTC6602-2 15MHz Filter, Single-Ended Input, Low Power Mode 25MHz Filter, Single-Ended Input, Low Power Mode -50 DISTORTION COMPONENT (dBc) DISTORTION COMPONENT (dBc) -60 -70 -80 -90 -100 -110 -120 -40 -50 -60 -70 -80 -90 -100 -110 -120 1 10 FREQUENCY (MHz) 100 66012 TA01a LTC6601-1 HD2 LTC6601-2 HD2 LTC6601-1 HD3 LTC6601-2 HD3 LTC6601-1 HD2 LTC6601-2 HD2 LTC6601-1 HD3 LTC6601-2 HD3 1 10 FREQUENCY (MHz) 100 66012 TA01b 66012f 1 LTC6601-2 ABSOLUTE MAXIMUM RATINGS (Note 1) PIN CONFIGURATION TOP VIEW IN4+ C5 C6 C7 C8 15 OUT- 14 V+ 21 13 V- 12 VOCM 11 OUT+ 6 IN4- 7 C1 8 C2 9 10 C3 C4 20 19 18 17 16 IN2+ 1 IN1+ - Total Supply Voltage (V + to V - ) ...............................5.5V Input Voltage (Any Pin) (Note 2) ..V + + 0.3V to V - -0.3V Input Current (VOCM, BIAS)..................................10mA Input Current (Pins 1, 5) (Note 2) ........................20mA Input Current (Pins 2, 4) (Note 2) ........................30mA Input Current (Pins 6, 20) (Note 2) ......................15mA Input Current (Pins 7, 8, 9, 10, 16, 17, 18, 19) (Note 2)................................................................10mA Output Short-Circuit Duration (Note 3) ............ Indefinite Operating Temperature Range (Note 4)....-40C to 85C Specified Temperature Range (Note 5) ....-40C to 85C Junction Temperature ........................................... 150C Storage Temperature Range...................-65C to 150C 2 BIAS 3 IN1 4 IN2- 5 UF PACKAGE 20-LEAD (4mm 4mm) PLASTIC QFN TJMAX = 150C, JA = 37C/W, JC = 4.3C/W EXPOSED PAD (PIN 21) IS V-, MUST BE SOLDERED TO PCB ORDER INFORMATION LEAD FREE FINISH LTC6601CUF-2#PBF LTC6601IUF-2#PBF TAPE AND REEL LTC6601CUF-2#TRPBF LTC6601IUF-2#TRPBF PART MARKING* 66012 66012 PACKAGE DESCRIPTION 20-Lead (4mm x 4mm) Plastic QFN 20-Lead (4mm x 4mm) Plastic QFN TEMPERATURE RANGE 0C to 70C -40C to 85C Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container. For more information on lead free part marking, go to: http://www.linear.com/leadfree/ For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/ DC ELECTRICAL CHARACTERISTICS + The l denotes the specifications which apply over the full operating - + SYMBOL VOSDIFF (Note 6) VOSDIFF/T (Note 6) RIN (Note 14) PARAMETER Amplifier Differential Offset Voltage (Input Referred) Ampifier Differential Offset Voltage Drift (Input Referred) CONDITIONS VS = 2.7V to 5.25V, BIAS = Floating BIAS = V+ VS = 2.7V to 5.25V l l temperature range, otherwise specifications are at TA = 25C. V = 3V, V = 0V, VINCM = VOCM = mid-supply, BIAS tied to V or floating, ILOAD = 0, RBAL = 100k. The filter is configured for a gain of 1 unless otherwise noted. VS is defined as (V+ - V-). VOUTCM is defined as (VOUT+ + VOUT-)/2. VINCM is defined as (VINP + VINM)/2. VOUTDIFF is defined as (VOUT+ - VOUT-). VINDIFF is defined as (VINP - VINM). See Figure 1. MIN TYP 0.25 0.25 1 MAX 2 1.25 UNITS mV mV V/C Input Resistance, BIAS = V+ Single Ended Input Resistance, Pin 2 or Pin 4 VS = 3V Differential Input Resistance VS = 3V 133 200 66012f 2 LTC6601-2 DC ELECTRICAL CHARACTERISTICS + The l denotes the specifications which apply over the full operating - + SYMBOL RIN (Note 14) IB (Note 7) IOS (Note 7) VINCM (Note 8) PARAMETER CONDITIONS l temperature range, otherwise specifications are at TA = 25C. V = 3V, V = 0V, VINCM = VOCM = mid-supply, BIAS tied to V or floating, ILOAD = 0, RBAL = 100k. The filter is configured for a gain of 1 unless otherwise noted. VS is defined as (V+ - V-). VOUTCM is defined as (VOUT+ + VOUT-)/2. VINCM is defined as (VINP + VINM)/2. VOUTDIFF is defined as (VOUT+ - VOUT-). VINDIFF is defined as (VINP - VINM). See Figure 1. MIN TYP 0.25 -25 -50 -12.5 -25 1 1 0 0 5 10 MAX UNITS A A A A Input Resistance Match, BIAS = V+ Single Ended Input Resistance, Pin 2 or Pin 4 VS = 3V Internal Amplifier Input Bias Internal Amplifier Input Offset Input Signal Common Mode Range (VINP + VINM)/2 BIAS = V+, VOCM = 2.5V BIAS = V+, VOCM = 1.5V BIAS Pin Floating, VOCM = 2.5V BIAS Pin Floating, VOCM = 1.5V CMRRI (Notes 9, 14) CMRRO (Notes 9, 14) PSRR (Note 10) Input Common Mode Rejection Ratio (Amplifier Input Referred) VINCM/VOSDIFF VINCM = 2.5V Output Common Mode Rejection Ratio (Amplifier Input Referred) VOCM/VOSDIFF VOCM = 1V Power Supply Rejection Ratio (Amplifier Input Referred) VS /VOSDIFF BIAS Pin Floating BIAS = V+ VS = 2.7V to 5V VS = 2.7V to 5V BIAS = Floating BIAS = V+ BIAS = Floating BIAS = V+ l l l l VS = 5V VS = 3V VS = 5V VS = 3V l l l l 0 0 0 0 4.7 1.7 4.8 1.8 V V V V VS = 5V 74 dB VS = 5V 70 dB VS = 2.7V to 5V VS = 2.7V to 5V l l l 58 58 40 94 81 51 1 dB dB dB V/V 1.0 -40 -40 30 30 % dB dB mV mV V/C V/C 1.8 4 1.7 4 V V V V k V PSRRCM (Note 10) Common Mode Power Supply Rejection Ratio (VS /VOSCM) VS = 2.7V to 5V gcm Common Mode Gain (VOUTCM/VOCM) VOCM = 2V Common Mode Gain Error = 100 * (gcm - 1) VOCM = 2V BAL Output Balance (VOUTCM/VOUTDIFF) Single-Ended Input Differential Input Common Mode Offset Voltage (VOUTCM - VOCM) Common Mode Offset Voltage Drift (VOUTCM - VOCM) Output Signal Common Mode Range (Voltage Range for the VOCM Pin) VS = 5V VS = 5V VOUTDIFF = 2V VS = 5V VS = 5V VS = 2.7V to 5V VS = 2.7V to 5V VS = 2.7V to 5V VS = 2.7V to 5V VS = 3V VS = 5V VS = 3V VS = 5V VS = 3V VS = 3V BIAS = Floating BIAS = V+ BIAS = Floating BIAS = V+ BIAS Pin Floating BIAS Pin Floating BIAS = V+ BIAS = V+ l l l l l l l l l l l l l 0.3 -58 -62 15 15 20 20 1.1 1.1 1.1 1.1 5 1.475 7 1.5 VOSCM VOSCM/T VOUTCMR (Note 8) RINVOCM VMID Input Resistance, VOCM Pin Voltage at the VOCM PIn 9 1.525 66012f 3 LTC6601-2 DC ELECTRICAL CHARACTERISTICS + The l denotes the specifications which apply over the full operating - + SYMBOL VOUT PARAMETER Output Voltage, High, Either Output Pin (Note 11) CONDITIONS VS = 3V, IL = 0mA, BIAS Pin Floating VS = 3V, IL = -5mA, BIAS Pin Floating VS = 3V, IL = -20mA, BIAS Pin Floating VS = 5V, IL = 0mA, BIAS Pin Floating VS = 5V, IL = -5mA, BIAS Pin Floating VS = 5V, IL = -20mA, BIAS Pin Floating VS = 3V, IL = 0mA VS = 3V, IL = -5mA VS = 3V, IL = -20mA VS = 5V, IL = 0mA VS = 5V, IL = -5mA VS = 5V, IL = -20mA Output Voltage, Low, Either Output Pin (Note 11) BIAS = V+ BIAS = V+ BIAS = V+ BIAS = V+ BIAS = V+ BIAS = V+ l l l l l l l l l l l l l l l l l l l l l l l l l l l l l l l l l l l l l l l l l temperature range, otherwise specifications are at TA = 25C. V = 3V, V = 0V, VINCM = VOCM = mid-supply, BIAS tied to V or floating, ILOAD = 0, RBAL = 100k. The filter is configured for a gain of 1 unless otherwise noted. VS is defined as (V+ - V-). VOUTCM is defined as (VOUT+ + VOUT-)/2. VINCM is defined as (VINP + VINM)/2. VOUTDIFF is defined as (VOUT+ - VOUT-). VINDIFF is defined as (VINP - VINM). See Figure 1. MIN TYP 240 290 470 370 430 650 245 285 415 350 390 550 110 120 170 150 170 225 120 135 195 175 200 270 45 60 2.7 15.8 16 16.7 32 32.2 33 0.4 0.45 0.65 V- V- + 1.0 V- + 2.3 100 V- + 1.05 150 V- + 1.15 400 400 65 90 5.25 23 23.5 24.5 41 41.5 43 1 1.1 1.8 V- + 0.4 V- + 1.5 V+ 200 V- + 1.25 MAX 450 525 850 675 775 1100 450 525 750 625 700 1000 200 225 300 270 300 400 225 250 350 325 360 475 UNITS mV mV mV mV mV mV mV mV mV mV mV mV mV mV mV mV mV mV mV mV mV mV mV mV mA mA V mA mA mA mA mA mA mA mA mA V V V k V ns ns VS = 3V, IL = 0mA, BIAS Pin Floating VS = 3V, IL = 5mA, BIAS Pin Floating VS = 3V, IL = 20mA, BIAS Pin Floating VS = 5V, IL = 0mA, BIAS Pin Floating VS = 5V, IL = 5mA, BIAS Pin Floating VS = 5V, IL = 20mA, BIAS Pin Floating VS = 3V, IL = 0mA VS = 3V, IL = 5mA VS = 3V, IL = 20mA VS = 5V, IL = 0mA VS = 5V, IL = 5mA VS = 5V, IL = 20mA BIAS = V+ BIAS = V+ BIAS = V+ BIAS = V+ BIAS = V+ BIAS = V+ ISC VS IS Output Short-Circuit Current, Either Output Pin (Note 12) Supply Voltage Range Supply Current, BIAS Pin Floating VS = 3V VS = 5V VS = 2.7V VS = 3V VS = 5V VS = 2.7V VS = 3V VS = 5V VS = 2.7V VS = 3V VS = 5V VS = 2.7V to 5V VS = 2.7V to 5V VS = 2.7V to 5V VS = 2.7V to 5V VS = 2.7V to 5V VS = 3V, VSHDN = 0.25V to 3V VS = 3V, VSHDN = 3V to 0.25V Supply Current, BIAS Pin Tied to V+ ISHDN Supply Current, BIAS Pin Tied to V- VBIASSD VBIASLP (Note 13) VBIASHP RBIAS VBIAS tON tOFF BIAS Input Pin Range for Shutdown BIAS Input for Low Power Operation BIAS Input for High Performance Operation BIAS Input Resistance BIAS Float Voltage Turn-On Time Turn-Off Time 66012f 4 LTC6601-2 AC ELECTRICAL CHARACTERISTICS + The l denotes the specifications which apply over the full operating - + SYMBOL GAIN PARAMETER Filter Gain, See Figure 2, BIAS Pin Floating (Remaining AC Measurements Relative to 1MHz) CONDITIONS VIN = 0.25V, fTEST = DC (Note 14) VIN = 600mVP-P, fTEST = 1MHz VIN = 600mVP-P, fTEST = 2MHz VIN = 600mVP-P, fTEST = 5MHz VIN = 600mVP-P, fTEST = 10MHz VIN = 600mVP-P, fTEST = 14.45MHz VIN = 600mVP-P, fTEST = 20MHz VIN = 600mVP-P, fTEST = 50MHz VIN = 0.25V, fTEST = DC VIN = 600mVP-P, fTEST = 1MHz VIN = 600mVP-P, fTEST = 2MHz VIN = 600mVP-P, fTEST = 5MHz VIN = 600mVP-P, fTEST = 10MHz VIN = 600mVP-P, fTEST = 14.45MHz VIN = 600mVP-P, fTEST = 20MHz VIN = 600mVP-P, fTEST = 50MHz BW = 100MHz BW = 20MHz BW = 100MHz BW = 20MHz HD2, Single-Ended Input HD3, Single-Ended Input HD2, Differential Input HD3, Differential Input VIN = 0.25V, fTEST = DC (Note 14) VIN = 600mVP-P, fTEST = 1MHz VIN = 600mVP-P, fTEST = 2MHz VIN = 600mVP-P, fTEST = 5MHz VIN = 600mVP-P, fTEST = 10MHz VIN = 600mVP-P, fTEST = 14.45MHz VIN = 600mVP-P, fTEST = 20MHz VIN = 600mVP-P, fTEST = 50MHz VIN = 0.25V, fTEST = DC VIN = 600mVP-P, fTEST = 1MHz VIN = 600mVP-P, fTEST = 2MHz VIN = 600mVP-P, fTEST = 5MHz VIN = 600mVP-P, fTEST = 10MHz VIN = 600mVP-P, fTEST = 14.45MHz VIN = 600mVP-P, fTEST = 20MHz VIN = 600mVP-P, fTEST = 50MHz BW = 100MHz BW = 20MHz BW = 100MHz BW = 20MHz HD2, Single-Ended Input HD3, Single-Ended Input HD2, Differential Input HD3, Differential Input l l l l l l l l l l l l l l l l l l l l l l l l l l l l l l l l temperature range, otherwise specifications are at TA = 25C. V = 3V, V = 0V, VINCM = VOCM = mid-supply, VBIAS is tied to V or floating, unless otherwise noted. (See Figure 2 for the AC test configuration.) VS is defined as (V+ - V-). VOUTCM is defined as (VOUT+ + VOUT-)/2. VICM is defined as (VINP + VINM)/2. VOUTDIFF is defined as (VOUT+ - VOUT-). VINDIFF is defined as (VINP - VINM). MIN -0.25 -0.08 -0.01 -0.54 -3.00 -7.55 -23.55 -6.0 -12.5 -31.8 -70.1 -103.5 -130.7 TYP 0.05 0 0.02 0.11 -0.34 -2.50 -6.55 -21.55 0 -5.5 -11.3 -29.3 -65.2 -97.5 -125.1 -173.6 154 135 73 74 -60 -79 -65 -77 -120 -0.25 -0.08 -0.01 -0.54 -2.75 -7.14 -23.70 -6.0 -12.2 -31.2 -68.8 -101.5 -128.4 0.05 0 0.02 0.11 -0.34 -2.35 -6.24 -21.70 0 -5.4 -11 -28.7 -63.8 -95.5 -123.4 -169.3 108 97 76 77 -67.5 -90 -70 -90 -120 0.25 0.12 0.23 -0.14 -1.95 -5.34 -19.70 -4.8 -9.8 -26.2 -58.8 -89.5 -118.4 MAX 0.25 0.12 0.23 -0.14 -2.00 -5.55 -19.55 -4.8 -10.1 -26.8 -60.1 -91.5 -120.7 UNITS dB dB dB dB dB dB dB dB Deg Deg Deg Deg Deg Deg Deg Deg VRMS VRMS dB dB dBc dBc dBc dBc ppm/C dB dB dB dB dB dB dB dB Deg Deg Deg Deg Deg Deg Deg Deg VRMS VRMS dB dB dBc dBc dBc dBc ppm/C PHASE Filter Phase, See Figure 2, BIAS Pin Floating NOISE SNR Distortion Output Noise, See Figure 2, BIAS Pin Floating BIAS Pin Floating VIN = 2VP-P , 10MHz, BIAS Pin Floating fO TC GAIN Cutoff Frequency Temperature Coefficient Filter Gain, See Figure 2, BIAS Pin Tied to V+, AC Gain Measurements Relative to 1MHz PHASE Filter Phase, See Figure 2, BIAS Pin Tied to V+ NOISE SNR Wide Band Output Noise, 14.45MHz Cutoff, BIAS Pin Tied to V+ BIAS Pin Tied to V+ DISTORTION VIN = 2VP-P , 10MHz, BIAS Pin Tied to V+ fO TC Cutoff Frequency Temperature Coefficient 66012f 5 LTC6601-2 ELECTRICAL CHARACTERISTICS Note 1: Stresses beyond those listed under the Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. Note 2: All pins are protected by steering diodes to either supply. If any pin is driven beyond the part's supply voltage, the excess input current (current in excess of what it takes to drive that pin to the supply rail) should be limited to less than 10mA. Note 3: A heat sink may be required to keep the junction temperature below the Absolute Maximum Rating when the output is shorted indefinitely. Long-term application of output currents in excess of the Absolute Maximum Ratings may impair the life of the device. Note 4: The LTC6601C/LTC6601I are guaranteed functional over the operating temperature range -40C to 85C. Note 5: The LTC6601C is guaranteed to meet specified performance from 0C to 70C. The LTC6601C is designed, characterized, and expected to meet specified performance from -40C to 85C but is not tested or QA sampled at these temperatures. The LTC6601I is guaranteed to meet specified performance from -40C to 85C. Note 6: Output referred voltage offset is a function of the low frequency gain of the LTC6601. To determine output referred voltage offset, or output voltage offset drift, multiply this specification by the noise gain (1 + GAIN). See Applications Information for more details. Note 7: Input bias current is defined as the average of the currents flowing into the noninverting and inverting inputs of the internal amplifier and is calculated from measurements made at the pins of the IC. Input offset current is defined as the difference of the currents flowing into the noninverting and inverting inputs of the internal amplifier and is calculated from measurements made at the pins of the IC. Note 8: Input common mode range is tested using the test circuit of Figure 1 by measuring the differential DC gain with VICM = mid-supply, and with VICM at the input common mode range limits listed in the Electrical Characteristics table, verifying the differential gain has not deviated from the mid-supply common mode input case by more than 1%, and the common mode offset (VOCMOS) has not deviated from the mid-supply common mode offset by more than 20mV. The voltage range for the output common mode range is tested using the test circuit of Figure 1 by measuring the differential DC gain with VOCM = mid-supply, and again with a voltage set on the VOCM pin at the Electrical Characteristics table limits, checking the differential gain has not deviated from the mid-supply common mode input case by more than 1%, and that the common mode offset (VOCMOS) has not deviated by more than 20mV from the mid-supply case. Note 9: Input CMRR is defined as the ratio of the change in the input common mode voltage at the amplifier input to the change in differential input referred voltage offset. Output CMRR is defined as the ratio of the change in the voltage at the VOCM pin to the change in differential input referred voltage offset. Note 10: Power supply rejection (PSRR) is defined as the ratio of the change in supply voltage to the change in differential input referred voltage offset. Common mode power supply rejection (PSRRCM) is defined as the ratio of the change in supply voltage to the change in the common mode offset, VOUTCM /VOCM. Note 11: Output swings are measured as differences between the output and the respective power supply rail. Note 12: Extended operation with the output shorted may cause junction temperatures to exceed the 150C limit and is not recommended. Note 13: Floating the BIAS pin will reliably place the part into the halfpower mode. The pin does not have to be driven. Care should be taken, however, to prevent external leakage currents in or out of this pin from pulling the pin into an undesired state. Note 14: The variable contact resistance of the high speed test equipment limits the accuracy of this test. These parameters only show a typical value, or conservative minimum and maximum value. 66012f 6 LTC6601-2 TYPICAL PERFORMANCE CHARACTERISTICS Low Power Supply Current vs Temperature and Supply Voltage 18.0 VINCM = VOCM = MID-SUPPLY BIAS PIN FLOATING 17.5 17.0 ICC (mA) ICC (mA) 16.5 3V 16.0 15.5 15.0 -50 2.7V 5V 32 3V 31 2.7V ICC (mA) 5V 33 34 35 VINCM = VOCM = MID-SUPPLY BIAS PIN TIED TO V+ High Performance Supply Current vs Temperature and Supply Voltage 0.8 0.7 0.6 0.5 0.4 Shutdown Supply Current vs Temperature and Supply Voltage VINCM = VOCM = MID-SUPPLY BIAS PIN TIED TO V - 5V 3V 0.3 0.2 0.1 2.7V -25 25 75 0 50 TEMPERATURE (C) 100 125 30 -50 -25 25 75 0 50 TEMPERATURE (C) 100 125 0 -50 -25 25 75 0 50 TEMPERATURE (C) 100 125 66012 G01 66012 G02 66012 G03 Supply Current vs Bias Pin Voltage and Temperature 50 VINCM = VOCM = MID-SUPPLY VS = 3V 40 1 Shutdown Supply Current vs Supply Voltage and Temperature 100 125C 10 -40C 0.1 25C ICC (mA) 1 Low Power Mode Supply Current vs Supply Voltage and Temperature 125C ICC (mA) ICC (mA) 30 20 -40C 0.1 25C 0.01 0.01 10 -40C 25C 125C 0 1 2 3 0.5 1.5 2.5 BIAS PIN VOLTAGE WITH RESPECT TO V- (V) 66012 G04 VINCM = VOCM = MID-SUPPLY BIAS PIN TIED TO V- 0.001 0 1 2 4 3 SUPPLY VOLTAGE (V) 5 66012 G05 VINCM = VOCM = MID-SUPPLY BIAS PIN FLOATING 0.001 0 1 2 4 3 SUPPLY VOLTAGE (V) 5 66012 G06 0 High Performance Supply Current vs Supply Voltage and Temperature 100 125C VOS INPUT REFERRED (mV) 10 -40C 1.00 High Performance Mode Differential VOS vs Temperature VS = 3V 0.75 VINCM = VOCM = MID-SUPPLY BIAS PIN TIED TO V+ 0.50 5 REPRESENTATIVE UNITS 0.25 0.00 -0.25 -0.50 -0.75 -1.00 -50 -25 0 50 75 25 TEMPERATURE (C) 100 125 1.00 Low Power Mode Differential VOS vs Temperature VS = 3V 0.75 VINCM = VOCM = MID-SUPPLY BIAS PIN FLOATING 0.50 5 REPRESENTATIVE UNITS 0.25 0.00 -0.25 -0.50 -0.75 -1.00 -50 -25 0 50 75 25 TEMPERATURE (C) 100 125 ICC (mA) 1 0.1 25C 0.01 VINCM = VOCM = MID-SUPPLY BIAS PIN TIED TO V+ 0.001 0 1 3 2 4 SUPPLY VOLTAGE (V) 5 66012 G07 66012 G08 VOS INPUT REFERRED (mV) 66012 G09 66012f 7 LTC6601-2 TYPICAL PERFORMANCE CHARACTERISTICS High Performance Common Mode VOS vs Temperature 10 15 10 5 VOSCM (mV) 5 VOSCM (mV) 0 0 -5 -5 V = 3V S VINCM = VOCM = MID-SUPPLY BIAS PIN TIED TO V+ 5 REPRESENTATIVE UNITS -10 -50 -25 0 50 75 25 TEMPERATURE (C) VS = 3V -10 VINCM = VOCM = MID-SUPPLY BIAS PIN FLOATING 5 REPRESENTATIVE UNITS -15 -50 -25 0 50 75 25 TEMPERATURE (C) -25 VS = 3V VINCM = VOCM = MID-SUPPLY -25 0 50 75 25 TEMPERATURE (C) 100 125 IBIAS (A) -15 HIGH PERFORMANCE MODE (BIAS PIN TIED TO V+) Low Power Common Mode VOS vs Temperature -5 Internal Amplifier Input Bias Current vs Temperature LOW POWER MODE (BIAS PIN FLOATING) -10 -20 100 125 100 125 -30 -50 66012 G10 66012 G11 66012 G12 BIAS Pin Input Resistance vs Temperature 200 VS = 3V VINCM = VOCM = MID-SUPPLY 175 FLOAT VOLTAGE (V) RESISTANCE () 1.15 1.20 BIAS Pin Float Voltage vs Temperature 1.0050 VS = 3V VINCM = VOCM = MID-SUPPLY RESISTANCE/RNOMINAL (/) Filter Input Resistance vs Temperature VS = 3V VINCM = VOCM = MID-SUPPLY RNOMINAL = 200 DIFFERENTIAL 1.0025 RNOMINAL = 133.3 SINGLE-ENDED SEE FIGURE 1 FOR CONFIGURATION 150 1.10 1.0000 125 1.05 0.9975 SINGLE-ENDED DIFFERENTIAL -25 0 50 75 25 TEMPERATURE (C) 100 125 100 -50 -25 0 50 75 25 TEMPERATURE (C) 100 125 1.00 -50 -25 0 50 75 25 TEMPERATURE (C) 100 125 0.9950 -50 66012 G13 66012 G14 66012 G15 Low Frequency Gain vs Temperature 1.010 VS = 3V VINCM = VOCM = MID-SUPPLY 5 REPRESENTATIVE UNITS 10 High Performance Mode Frequency Response of 12 Possible Filter Configurations 10 Low Power Mode Frequency Response of 12 Possible Filter Configurations 1.005 0 GAIN (V/V) 1.000 GAIN (dB) GAIN (dB) 0 -10 -10 0.995 -20 VS = 3V VINCM = VOCM = MID-SUPPLY BIAS PIN TIED TO V+ 1 10 FREQUENCY (MHz) 100 66012 G17 -20 VS = 3V VINCM = VOCM = MID-SUPPLY BIAS PIN FLOATING 1 10 FREQUENCY (MHz) 100 66012 G18 0.990 -50 -25 0 50 75 25 TEMPERATURE (C) 100 125 -30 0.1 -30 0.1 66012 G16 66012f 8 LTC6601-2 TYPICAL PERFORMANCE CHARACTERISTICS High Performance Mode Gain and Phase Repeatability of 10 Random Units 0.20 VS = 3V 0.15 VINCM = VOCM = MID-SUPPLY BIAS PIN TIED TO V+ SEE FIGURE 1 0.10 MAX - AVERAGE 0.05 MAX - AVERAGE 0 -0.05 -0.10 -0.15 -0.20 0.1 1 10 FREQUENCY (MHz) MIN - AVERAGE MIN - AVERAGE Low Power Mode Gain and Phase Repeatability of 10 Random Units 4 3 GAIN DEVIATION (dB) 2 1 0 -1 -2 -3 -4 100 PHASE DEVIATION (DEG) 0.20 VS = 3V 0.15 VINCM = VOCM = MID-SUPPLY BIAS PIN FLOATING SEE FIGURE 1 0.10 MAX - AVERAGE 0.05 MAX - AVERAGE 0 -0.05 -0.10 -0.15 -0.20 0.1 1 10 FREQUENCY (MHz) MIN - AVERAGE MIN - AVERAGE 4 3 2 1 0 -1 -2 -3 -4 100 66012 G20 PHASE DEVIATION (DEG) GAIN DEVIATION (dB) 66012 G19 High Performance Mode Gain Error of 10 Random Units Normalized to 1MHz 3 VS = 3V VICM = VOCM = MID-SUPPLY 2 BIAS PIN TIED TO V+ 10 RANDOM UNITS PLOTTED TA = 25C 1 +SPECIFICATION 0 -1 -SPECIFICATION -2 -3 -2 -3 1 10 FREQUENCY (MHz) 100 66012 G21 Low Power Mode Gain Error of 10 Random Units Normalized to 1MHz 3 VS = 3V VICM = VOCM = MID-SUPPLY 2 BIAS PIN FLOATING 10 RANDOM UNITS PLOTTED TA = 25C 1 +SPECIFICATION 0 -1 8 High Performance Mode Phase Error of 10 Random Units VICM = VOCM = MID-SUPPLY 6 VS = 3V TA = 25C PHASE ERROR (DEG) 4 2 0 -2 -4 -SPECIFICATION +SPECIFICATION GAIN ERROR (dB) GAIN ERROR (dB) -SPECIFICATION 1 10 FREQUENCY (MHz) 100 66012 G22 -6 BIAS PIN TIED TO V+ 10 RANDOM UNITS PLOTTED -8 1 10 FREQUENCY (MHz) 100 66012 G23 Low Power Mode Phase Error of 10 Random Units 8 5 4 3 2 VOUTDIFF (V) 1 0 -1 -2 -3 -4 -5 100 66012 G24 Turn On and Turn Off Transient Response VS = 5V 1.6 BIAS PIN 1.4 1.2 VOUTDIFF (V) 1.0 0.8 0.6 0.4 VOUTDIFF 0 1 2 3 4 TIME (s) 5 6 66012 G25 Pulse Response 2 VS = 3V VICM = VOCM = MID-SUPPLY 6 VS = 3V TA = 25C PHASE ERROR (DEG) 4 2 0 -2 -4 -SPECIFICATION +SPECIFICATION 1 VBIAS PIN (V) 0 -1 -6 BIAS PIN FLOATING 10 RANDOM UNITS PLOTTED -8 1 10 FREQUENCY (MHz) 0.2 0 -2 0 1 2 3 4 5 TIME (s) 6 7 8 66012 G26 66012f 9 LTC6601-2 TYPICAL PERFORMANCE CHARACTERISTICS Differential Output Noise 100 NOISE SPECTRAL DENSITY (nV/Hz) VS = 3V 1000 SPECTRAL DENSITY, BIAS TIED TO V+ INTEGRATED NOISE (VRMS) HARMONIC (dBc) 100 SPECTRAL DENSITY, BIAS PIN FLOATING INTEGRATED NOISE, 1 BIAS TIED TO V+ -60 Distortion vs Frequency VS = 5V VIN = 2VP-P INPUT -70 VICM = VOCM = MID-SUPPLY BIAS PIN TIED TO V+ -80 -90 -100 -110 -120 1 100 66012 G27 Distortion vs Frequency HD2 -50 VS = 5V V = 2VP-P INPUT -60 VIN = V ICM OCM = MID-SUPPLY -70 BIAS PIN FLOATING -80 HD3 -90 -100 -110 HD2 HD3 10 INTEGRATED NOISE, BIAS PIN FLOATING 0.1 0.001 0.01 0.1 1 FREQUENCY (MHz) 10 HARMONIC (dBc) 10 -130 0.1 SINGLE ENDED INPUT DIFFERENTIAL INPUT 1 10 100 FREQUENCY (MHz) 66012 G28 -120 0.1 SINGLE ENDED INPUT DIFFERENTIAL INPUT 1 10 FREQUENCY (MHz) 100 66012 G29 % Change of fO vs Temperature 0.5 0.5 0 0 CHANGE OF fO (%) -0.5 GAIN (dB) -0.5 Passband Gain and Phase vs Temperature 0 -15 GAIN ERROR (dB) -30 PHASE (DEG) PHASE -1.0 -1.5 -2.0 VS = 3V VICM = VOCM = MID-SUPPLY -2.5 BIAS PIN TIED TO V+ TEMPERATURES PLOTTED: -45C, -10C, 25C, 70C, 95C, 125C -3.0 1 10 FREQUENCY (MHz) 66012 G31 Gain Error Relative to 1MHz vs Temperature 3 VS = 3V VICM = VOCM = MID-SUPPLY 2 BIAS PIN TIED TO V+ TEMPERATURES PLOTTED: -45C, -10C, 25C, 1 70C, 95C, 125C +SPECIFICATION 0 -1 -SPECIFICATION -2 -3 GAIN -45 -60 -75 -90 -1.0 -1.5 -2.0 -50 -25 0 50 75 25 TEMPERATURE (C) 100 125 -105 1 10 FREQUENCY (MHz) 100 66012 G32 66012 G30 Phase Error vs Temperature 15 VS = 3V VICM = VOCM = MID-SUPPLY 10 BIAS PIN TIED TO V+ TEMPERATURES PLOTTED: -45C, -10C, 25C, 5 70C, 95C, 125C +SPECIFICATION 0 -5 900 800 700 600 FREQUENCY Normalized 100 Resistor Trim AVERAGE = 100 STD. DEV = 0.19 1000 Normalized 125 Resistor Trim AVERAGE = 125 900 STD. DEV = 0.22 800 700 FREQUENCY 600 500 400 300 200 100 PHASE ERROR (dB) 500 400 300 200 -SPECIFICATION -10 100 -15 1 10 FREQUENCY (MHz) 100 66012 G33 0 0.993 0.997 1.001 1.005 NORMALIZED RESISTANCE 1.009 66012 G34 0 0.99 0.994 0.998 1.002 1.006 NORMALIZED RESISTANCE 1.01 66012 G35 66012f 10 LTC6601-2 TYPICAL PERFORMANCE CHARACTERISTICS Normalized 200 Resistor Trim 1000 AVERAGE = 200 900 STD. DEV = 0.37 800 700 FREQUENCY FREQUENCY 600 500 400 300 200 100 0 0.99 0.994 0.998 1.002 1.006 NORMALIZED RESISTANCE 1.01 66012 G36 Normalized Input 400 Resistor Trim 900 AVERAGE = 400.01 800 STD. DEV = 1.0 700 FREQUENCY 600 500 400 300 200 100 0 0.99 0.994 0.998 1.002 1.006 NORMALIZED RESISTANCE 1.01 66012 G37 Normalized Feedback 400 Resistor Trim 1000 AVERAGE = 400.01 900 STD. DEV = 0.87 800 700 600 500 400 300 200 100 0 0.99 0.994 0.998 1.002 1.006 NORMALIZED RESISTANCE 1.01 66012 G38 Normalized 21.1pF Capacitor Trim 1200 1000 800 FREQUENCY 600 400 200 0 AVERAGE = 21.1pF STD. DEV = 0.07pF 1000 Normalized 33.3pF Capacitor Trim AVERAGE = 33.3pF 900 STD. DEV = 0.09pF 800 700 FREQUENCY 600 500 400 300 200 100 0 FREQUENCY 1200 1000 800 600 400 200 0 Normalized 48.2pF Capacitor Trim AVERAGE = 48.2pF STD. DEV = 0.08pF 0.984 0.990 0.997 1.003 1.009 NORMALIZED CAPACITANCE 1.015 66012 G39 0.988 0.993 0.999 1.005 1.010 NORMALIZED CAPACITANCE 1.016 0.992 0.995 0.998 1.001 1.004 1.007 1.010 NORMALIZED CAPACITANCE 66012 G41 66012 G40 Normalized 81.5pF Capacitor Trim 1000 AVERAGE = 81.5pF 900 STD. DEV = 0.1pF 800 700 FREQUENCY 600 500 400 300 200 100 0 0.993 0.996 0.999 1.002 1.004 1.007 1.010 NORMALIZED CAPACITANCE 66012 G42 Normalized 10.55pF Capacitor Trim 400 AVERAGE = 10.55pF 350 STD. DEV = 0.03pF 300 FREQUENCY FREQUENCY 250 200 150 100 50 0 0.987 0.991 0.996 1.000 1.005 1.009 1.014 NORMALIZED CAPACITANCE 66012 G43 Normalized 16.1pF Capacitor Trim 350 300 250 200 150 100 50 0 0.988 0.992 0.995 0.999 1.003 1.006 1.010 1.014 NORMALIZED CAPACITANCE 66012 G44 AVERAGE = 16.1pF STD. DEV = 0.05pF 66012f 11 LTC6601-2 PIN FUNCTIONS (Refer to the Block Diagram) IN1+, IN2+, IN4+ (Pins 2, 1, 20): Input to a trimmed 100, 200, 400 resistor which feeds a noninverting summing node. Can accept an input signal, be floated or tied to OUT-. For best performance, stray capacitance should be kept as low as possible by keeping printed circuit connections as short and direct as possible. If necessary, strip back the surrounding ground plane away from these pins. BIAS (Pin 3): Input to a three-state comparator whose three states allow the user to tailor amplifier power. The pin impedance appears as a 150k resistor whose default open-circuit potential is 1.15V with respect to the V- power supply. If BIAS is driven to within 0.4V of the V- supply, the amplifier is placed into a low power shutdown, consuming typically 450A. When BIAS is floated, the amplifier operates in its low power active state. Forcing the pin 2.3V above V- places the part into the high performance active state. See Applications Information for more detail. IN1-, IN2-, IN4- (Pins 4, 5, 6): Input to a trimmed 100, 200, 400 resistor which feeds an inverting summing node. Can accept an input signal, be floated or tied to OUT+. For best performance, it is highly recommended that stray capacitance be kept to as low as possible by keeping printed circuit connections as short and direct as possible, and if necessary, stripping back nearby surrounding ground plane away from these pins. C1, C2 (Pins 7, 8): Input to a trimmed 16.1pF 33.3pF , capacitor which feeds a noninverting summing node. Typically, either float or tie to OUT-. If either of these pins is tied to a low impedance source other than OUT-, a resistance of at least 25 should be placed in series. For best performance, it is highly recommended that stray capacitance be kept to as low as possible by keeping printed circuit connections as short and direct as possible, and if necessary, stripping back nearby surrounding ground plane away from these pins. C3, C4 (Pins 9, 10): Input to a trimmed 10.55pF 21.1pF , capacitor which feeds the amplifier inverting summing node. Typically, either float or tie to OUT+. For best performance, it is highly recommended that stray capacitance be kept to as low as possible by keeping printed circuit connections as short and direct as possible, and if necessary, stripping back nearby surrounding ground plane away from these pins. OUT+, OUT- (Pins 11, 15): Output Pins. Besides driving the internal feedback network, each pin can drive an additional 50 to ground with typical short-circuit current limiting of 65mA. Capacitive loading of these pins should be minimized by resistively decoupling the outputs from the load with at least 25. VOCM (Pin 12): Output Common Mode Reference Voltage. The voltage on VOCM sets the output common mode voltage level (which is defined as the average of the voltages on the OUT+ and OUT- pins). The VOCM pin is the midpoint of an internal resistive voltage divider between the supplies, developing a (default) mid-supply voltage potential to maximize output signal swing. The VOCM pin can be overdriven by an external voltage reference capable of driving the input impedance presented by the VOCM pin. The VOCM pin has an input resistance of approximately 7k to a mid-supply potential. It should be bypassed with a high quality ceramic bypass capacitor (for instance of X7R dielectric) of at least 0.01F (unless using symmetrical , split supplies, then connect directly to a low impedance, low noise ground plane) to minimize common mode noise from being converted to differential noise by impedance mismatches both externally and internally to the IC. 66012f 12 LTC6601-2 PIN FUNCTIONS (Refer to the Block Diagram) V+, V- (Pins 14, 13): Power Supply Pins. It is critical that close attention be paid to supply bypassing. For single supply applications (Pin 13 grounded), it is recommended that a high quality 0.1F surface mount ceramic bypass capacitor (X7R dielectric for instance) be placed between Pins 14 and 13, with direct short connections. Pin 13 should be tied directly to a low impedance ground plane with minimal routing. For dual (split) power supplies, it is recommended that at least two additional high quality 0.1F ceramic capacitors are used to bypass V+ to ground and V- to ground, again with minimal routing. For driving large loads (< 200), additional bypass capacitance may be added for optimal performance. Keep in mind that small geometry (e.g., 0603) surface mount ceramic capacitors have a much lower ESL than do leaded capacitors, and perform best in high speed applications. C7, C8 (Pins 17, 16): Input to a trimmed 10.55pF 21.1pF , capacitor which feeds the amplifier noninverting summing node. Typically, either float or tie to OUT-. For best performance, stray capacitance should be kept as low as possible by keeping printed circuit connections as short and direct as possible.If necessary, strip back the surrounding ground plane away from these pins. C5, C6 (Pins 19, 18): Input to a trimmed 16.1pF 33.3pF , capacitor which feeds an inverting summing node. Typically, either float or tie to OUT+. If either of these pins are tied to a low impedance source other than OUT+, a resistance of at least 25 should be placed in series. For best performance, it is highly recommended that stray capacitance be kept to as low as possible by keeping printed circuit connections as short and direct as possible, and if necessary, stripping back nearby surrounding reference plane away from these pins. Exposed Pad (Pin 21): Always tie the underlying Exposed Pad to V- (Pin 13). If split supplies are used, do not tie the pad to ground. Tie it to V-. 66012f 13 LTC6601-2 BLOCK DIAGRAM 20 IN4+ 19 C5 18 C6 17 C7 16 C8 400 16.1pF 33.3pF 81.5pF 400 1 IN2+ 200 10.55pF OUT- 21.1pF IN1+ 100 48.2pF V - + 2.3V 860 180k 3 BIAS 60k BIAS 180k 125 125 V- 860 14k 14k V+ 14 15 2 + - 48.2pF 13 VOCM 12 4 IN1- 100 21.1pF OUT+ 10.55pF 5 IN2- 200 400 81.5pF 11 400 16.1pF 33.3pF IN4- 6 7 C1 8 C2 9 C3 C4 10 66012 BD 66012f 14 LTC6601-2 TEST CIRCUITS 20 LTC6601-2 19 18 17 16 1 2 15 VOUT- 25 IL + VINP 14 V+ 0.1F 0.1F V- 0.1F VOCM 0.01F VOUT+ 25 RBAL - BIAS VINM 3 + - 13 VOUT(CM) 5V 6 9 10 11 12 13 VIN 14 15 16 1 2 3 7 17 BIAS -5V 1F VINM 4 5 3 LT6411 8 5 VINP 1F + 4 5 6 7 8 9 10 - LTC6601-2 20 19 18 1 2 6 7 8 12 RBAL IL 11 66012 F01 Figure 1. DC Test Circuit 17 16 15 VOUT- 100 1F 14 V+ 0.1F 0.1F V- 0.1F VOCM 0.01F VOUT+ 100 COILCRAFT TTWB-4-B + - 13 50 12 1F 11 9 10 66012 F02 Figure 2. AC Test Circuit (Frequency Response Testing) 66012f 15 LTC6601-2 APPLICATIONS INFORMATION FUNCTIONAL DESCRIPTION The LTC6601 is designed to make the implementation of high frequency fully-differential filtering functions very easy. A very low noise amplifier is surrounded by 8 precision matched resistors and 12 precision matched capacitors so that a myriad of filter transfer functions limited only by possible combinations and imagination can be configured by hard wiring pins. The amplifier itself is a wide band, low noise and low distortion fully-differential amplifier with accurate output phase balancing. It is optimized for driving low voltage, single-supply, differential input, analog-to-digital converters (ADCs). The LTC6601's outputs are capable of swinging rail-to-rail on supplies as low as 2.7V, which makes the amplifier ideal for converting ground referenced, single-ended signals into VOCM referenced differential signals. Unlike traditional op amps which have a single output, the LTC6601 has two outputs to process signals differentially. This allows for two times the signal swing in low voltage systems when compared to single-ended output amplifiers. The balanced differential nature of the amplifier and matched surrounding components provide even-order harmonic distortion cancellation, and less susceptibility to common mode noise (like power supply noise). The LTC6601 can be used as a single-ended input to differential output amplifier, or as a differential input to differential output amplifier. R2 C2 fO = Q= 1 2 R2 * R3 * C1* C2 C2 R3 * C1 R2 R2 R1 1 1+ 1+ GAIN * R3 C2 - R2 C1 Figure 3 shows the basic filter architecture. The Laplace transfer function from VINDIFF to VOUTDIFF is given by the following generalized equation for a 2nd order lowpass filter: VOUTDIFF = VINDIFF Gain 1+ s s2 + 2fO * Q ( 2f O )2 Both Gain and Q of the filter are based on component ratios, which match and track extremely well over temperature. The corner frequency of the filter is a function of an RC product. This RC product is trimmed to 1% (typical) and is not expected to drift by more than 1% from nominal over the entire temperature range -40C to 85C. As a result, fully differential filters with tight magnitude, phase tolerance and repeatability are achieved. Although Figure 3 implies a differential input, the LTC6601 easily accepts single-ended inputs to either input, and will faithfully replicate the signal at the output in differential form. The LTC6601's output common mode voltage, defined as the average of the two output voltages, is independent of the input common mode voltage, and is adjusted by applying a voltage on the VOCM pin. If the pin is left open, there is an internal resistive voltage divider, which develops a R1 R3 C1 +- VIN(DIFF) VOUT(DIFF) GAIN = -+ R1 R3 C1 fO * f3dB = 6089 * (3568 * Q 4 1788 * Q 2 + 447 + 1.287 * 105 * 2 * Q 2 507.6 * Q ) ( 1 ) ( C2 0.2236 * fO * Q= 2.109 * 105 * (9.891* 10 * f (16 * f * (8.29 * 10 * f 12 O 2 9 3dB 4 5.486 * 109 * fO4 + 120 * 5.526 * 109 * f3dB2 + 3.082 * 106 * fO2 2 ) 3dB + 4.127 * 109 * fO2 ) 6.638 * 1010 * f3dB 4 ) ) R2 66012 F03 Figure 3. Basic Filter Topology and Equations 66012f 16 LTC6601-2 APPLICATIONS INFORMATION potential halfway between the V+ and V- pins. Whenever this pin is not hard tied to a low impedance ground plane, a high quality ceramic capacitor should be used to bypass the VOCM pin to a low impedance ground plane (see Layout Considerations). The LTC6601's internal common mode feedback path forces accurate output phase balancing to reduce even order harmonics, and centers each individual output about the potential set by the VOCM pin. VOUT + + VOUT - VOUTCM = VOCM = 2 The outputs (OUT+ and OUT-) of the LTC6601 are capable of swinging rail-to-rail. They can source or sink up to approximately 75mA of current. Load capacitances should be decoupled with at least 25 of series resistance from each output. The LTC6601 Electrical Characteristics table specifies an input referred offset. This specification actually lumps voltage offsets due to offset bias currents (IOS), and amplifier voltage offset into one specification. To refer this specification to the output, you simply multiply the specification by the noise gain the LTC6601 is configured in: VOSODIFF = 1 + Gain where Gain is the closed loop gain in the particular filter application: Gain = R2 R1 (see the Electrical Characteristics table), and can be driven by an external source keeping in mind its equivalent input impedance and equivalent input voltage. If the BIAS pin is floated, care should be taken to control external leakage currents to this pin to under 1A to prevent putting the LTC6601 an undesired state. If BIAS is tied to the positive supply, the LTC6601 differential filter will be in a fully active state configured for highest performance (lowest noise and lowest distortion). If the BIAS pin is floated or left unconnected, the LTC6601 filter will be in a fully active state, with amplifier currents reduced and performance scaled back to preserve power consumption. If the BIAS pin is tied to the most negative supply (V-), the LTC6601 will be placed into a low power shutdown mode with amplifier outputs disabled. In this state, the LTC6601 draws approximately 450A. In low power shutdown, all internal biasing current sources are shut off, and the output pins, OUT+ and OUT-, will each appear as open collectors with a non-linear capacitor in parallel and steering diodes to either supply. The turn-on and turn-off time constant between states are on the order of 0.4s. Using this function to wire-OR outputs together is not recommended. General Design and Usage As levels of integration have increased and correspondingly, system supply voltages decreased, there has been a need for ADCs to process signals differentially in order to maintain good signal-to-noise ratios. These ADCs are typically supplied from a single supply voltage which can be as low as 3V (2.7V min), and will have an optimal common mode input range near mid-supply. The LTC6601 makes interfacing to these ADCs easy, by providing antialias filtering, single-ended to differential conversion and common mode level shifting (translation). Figure 3 shows a general application of this. The low frequency gain to VOUTDIFF from VIN is simply: VOUTDIFF = VOUT + - VOUT - R2 *V R1 INDIFF COMPONENT INPUT PIN PROTECTION All of the LTC6601 pins with the exception of V+ and V- are protected with steering diodes to either power supply. In the event that a pin is driven beyond the supply rails, the excess current should be limited to under 10mA to prevent damage to the IC. BIAS Pin The LTC6601 has a BIAS pin (Pin 3) whose function is to tailor both performance and power of the LTC6601. The pin has a Thevenin equivalent impedance of approximately 150k to a voltage source whose potential is 1.15V above the V- supply. This pin has fixed logic levels relative to V- The differential output voltage (VOUT+ - VOUT-) is completely independent of input and output common mode voltages, or the voltage at the common mode pin. This makes the 66012f 17 LTC6601-2 APPLICATIONS INFORMATION LTC6601 ideally suited for pre-amplification, level shifting and conversion of single-ended signals to differential output signals for driving differential input ADCs. INPUT IMPEDANCE Calculating the low frequency input impedance of the LTC6601 depends on how the inputs are driven (whether they are driven from a single-ended or a differential source). Figure 4 shows a simplified low frequency equivalent circuit of the LTC6601. For balanced input sources (VINP = -VINM), the low frequency input impedance is given by the equation: RINP = RINM = R1 The differential input impedance is simply: RINDIFF = 2 * R1 For single-ended inputs (VINM = 0), the input impedance actually increases over the balanced differential case due to the fact the summing node (at the junction of R1, R2 and R3) moves in phase with VINP to bootstrap the input impedance. Referring to Figure 4 with VINM = 0, the input impedance looking into either input is: RINP = RINM R1 1 R2 1- 2 * R1+ R2 Input and Output Common Mode Voltage Range The input common mode voltage is defined as the average of the two inputs: VINCM = VINP + VINM 2 The lower limit of the input common mode range is dictated by the ESD protection diodes at the input. While it is possible for the inputs to swing below V-, the diodes will conduct if the inputs are taken a diode drop below V-. The upper limit of the input common mode range varies as a function of the filter configuration (GAIN), VOCM potential, and whether or not the inputs are single-ended or differential. While it is possible to exceed the upper limit of the common mode range, doing so will degrade filter linearity. Referring to Figure 4, for linear operation, the summing junction where R1, R2 and R3 merge together should be prevented from swinging to within 1.4V of the V+ power supply. For the general case, the upper input common mode voltage limit should be constrained to: VOCM * R1 R2 + VINCM * V + - 1.4V R1+ R2 R1+ R2 Or equivalently: R1 R1 VINCM 1+ V + - 1.4V - *V R2 R2 OCM The specifications for input common mode range (VINCMR) are based on these constraints with R1 = R2 = 100, and VOCM = mid-supply. Substituting the numbers for a single 3V power supply, (V+ = 3V, V- = 0V) with VOCM =1.5V, and R1 = R2 = 100, into the above equation, the input common mode range (VINCMR) is between the two limits: 0V VINCM 1.7V which is as is specified for a 3V supply. ( ) R2 RINP + VINP R1 R3 - + VOUT- - - VINM R3 R1 RINM R2 VOUTDIFF - + + VOUT+ VOCM 0.1F 66012 F04 Figure 4. Input Impedance 66012f 18 LTC6601-2 APPLICATIONS INFORMATION Likewise, substituting the numbers for a single 5V power supply, (V+ = 5V, V- = 0V) with VOCM = 2.5V, and R1 = R2 = 100, into the above equation, the input common mode range (VINCMR) is between the two limits: 0V VINCM 4.7V The output common mode voltage is defined as the average of the two outputs: VOUTCM = VOCM = VOUT + + VOUT - 2 common mode voltage, it can be directly tied to the VOCM pin, but must be capable of driving the input impedance of the VOCM pin (RVOCM). This impedance can be assumed to be connected to a mid-supply potential. If an external reference drives the VOCM pin, it should still be bypassed with a high quality 0.01F or higher capacitor to a low impedance ground plane to filter any thermal noise and to prevent common mode signals on this pin from being inadvertently converted to differential signals. Noise Considerations When comparing the LTC6601 noise to other amplifiers, be sure to compare similar specifications. Competing devices often specify noise referred to the inputs of the amplifier. The input referred voltage noise of the LTC6601-2 is 4.7nV/Hz. In addition to the noise generated by the amplifier, the surrounding feedback resistors also contribute noise. A noise model is shown in Figure 5. The output spot noise generated by both the amplifier and the feedback components is governed by the equation: The VOCM pin sets this average by an internal common mode feedback loop which internally forces VOUT+ = -VOUT-. The output common mode range extends from 1.1 V above V- to 1V below V+. The VOCM pin sits in the middle of a voltage divider which sets the default midsupply open circuit potential. In single supply applications, where the LTC6601 is used to interface to an ADC, the optimal common mode input to the ADC is often determined by the ADC's reference. If the ADC makes a reference available for setting the input 2 2 2 2 R2 R2 R2 R2 2 2 2 eno = eni * 1+ + 2 * In * R2 + R3 * 1+ + 2 * enR1 * + 2 enR3 * 1+ + 2 * enR2 2 R1 R1 R1 R1 Substituting the equation for Johnson noise of a resistor (enR = 4kTR), and simplifying: 2 2 2 R2 R2 R2 R2 eno = eni * 1+ + 2 * In 2 * R22 + R32 * 1+ + 8 * k * T R2 1+ + R3 1+ R1 R1 R1 R1 66012f 19 LTC6601-2 APPLICATIONS INFORMATION enR22 R2 * enR12 R1 enR32 In+2 R3 * eni2 * enR32 enR12 R1 R3 In-2 * + eno2 * enR22 - * R2 66012 F05 * Figure 5. Differential Noise Model of the LTC6601 Table 1 lists the amplifier input referred noise for the LTC6601-2. Tables 2 to10 list the noise referred to the input pins of the IC for common configurations of the LTC6601-2. To determine the spot noise at the output, simply multiply the noise by the Gain = R2/R1. To estimate the integrated noise at the output, multiply the noise by the gain, and the square root of the noise bandwidth. The noise bandwidth depends on the filter configuration. For Figure 2, the noise bandwidth is 100MHz, or approximately 7 times the filter bandwidth. Improvements in SNR can be made by adding an additional RC filter at the output to band limit wide band noise before feeding ADCs. See the section "Interfacing the LTC6601 to ADC Converters" for more detail. Table 1. Amplifier (Input Referred) Noise Characteristics for the LTC6601-2 BIAS PIN PULLED TO V+ eni nV/Hz 4.7 in pA/Hz 3 BIAS PIN FLOATING eni nV/Hz 5.2 in pA/Hz 2.1 ceramic capacitor be used to bypass pin V+ to ground and V- to ground, again with minimal routing. For driving large differential loads (<200), additional bypass capacitance may be needed between V+ and V- for optimal performance. Note that small geometry (e.g., 0603) surface mount ceramic capacitors have a much higher self resonant frequency than capacitors with leads, and perform best in high speed applications. The VOCM pin should be bypassed to ground with a high quality ceramic capacitor whose value exceeds 0.01F , with direct, short connections. In split supply applications, the VOCM pin can be either bypassed to ground or directly hardwired to ground. Be careful not to violate the output common mode range specifications for the VOCM pin. Stray parasitic capacitances to unused component pins that set up the filter's characteristics, should be kept to an absolute minimum. This prevents deviations from the ideal frequency response. An ideal layout technique would be to remove the solder pads for the unused component pins, and strip away the ground plane underneath these pins to lower capacitance to an absolute minimum. Floating unused component pins which set up the filter characteristics will not reduce the reliability of the LTC6601. At the output, always keep in mind the differential nature of the LTC6601, and that it is critical that the load impedances seen by both outputs (stray or intended), should be as balanced and symmetric as possible. This will help preserve the natural balance of the LTC6601, which minimizes the generation of even order harmonics and preserves the rejection of common mode signals and noise. 66012f LAYOUT CONSIDERATIONS Because the LTC6601 is a very high speed amplifier, it is sensitive to both stray capacitance and stray inductance. It is critical that close attention be paid to supply bypassing. For single supply applications, it is recommended that a high quality 0.1F surface mount ceramic bypass capacitor be placed between Pins 14 and 13 with direct short connections. Pin 13 and the Exposed Pad, Pin 21, should be tied directly to a low impedance ground plane with minimal routing. For dual (split) power supplies, it is recommended that an additional high quality, 0.1F 20 LTC6601-2 APPLICATIONS INFORMATION INTERFACING THE LTC6601 TO ADC CONVERTERS The LTC6601's rail-to-rail differential output and adjustable output common mode voltage make the LTC6601 ideal for interfacing to low voltage, single supply, differential input ADCs. The sampling process of ADCs creates a sampling transient that is caused by the switching-in of the ADC sampling capacitor. The switching-in of this sampling capacitor momentarily "shorts" the output of the amplifier as charge is transferred between amplifier and sampling capacitor. The amplifier must recover and settle from this load transient before this acquisition period has ended, for a valid representation of the input signal. The LTC6601 will settle much more quickly from these periodic load impulses than it does from a 2V input step, but it is a good idea to add an RC network after the outputs of the LTC6601 to decouple the sampling transient of the ADC (See Figure 6). The capacitance of the decoupling network serves to provide the bulk of the charge during the sampling process, while the two resistors of the filter network are used to dampen and attenuate any transient induced by the ADC. The ADC's sampling bandwidth will often be much greater than that of the LTC6601, so having this discrete RC filter will give the additional benefit of band limiting broadband output noise. The selection of the RC time constant is trial and error for a given ADC, but the following guidelines are recommended. Choose an RC pole frequency greater than the cutoff frequency of the LTC6601. 80MHz RC filters are good for filtering broadband noise. Lower frequency RC filters improve SNR at the expense of settling time. The resistors in the decoupling network should be at least 25. Too much resistance in the decoupling network leaves insufficient settling time and will create a voltage divider between the dynamic input impedance of the ADC and the decoupling resistors. Using insufficient resistance might prevent proper dampening of the load transient caused by the sampling process, and prolong the time required for settling. In 16-bit applications, this will typically require a minimum of 11 RC time constants. It is recommended that the capacitor is chosen with low dielectric absorption (such as a C0G multilayer ceramic capacitor). LTC6601-2 20 19 18 17 16 1 + VIN 2 15 VOUT- R C1 CONTROL - BIAS 3 14 3V 0.1F 1F AIN+ C2 AIN- VCM 2.2F R C1 66012 F06 + - D15 * * D0 3.3V 1F 13 1F 4 5 12 VOUT+ VOCM 10nF GND 1F 11 6 7 8 9 10 t = R * (C1 + 2 * C2) Figure 6. Interfacing the LTC6601 to A/D Converters 66012f 21 LTC6601-2 APPLICATIONS INFORMATION A GALLERY OF BASIC FILTER TOPOLOGIES Tables 2 through 10 list (sorted by Gain) a hundred possible filter topologies that can be easily implemented with the LTC6601. The tables also list the LTC6601-2 approximate midband (1MHz) spot noise ein referred to the input resistor, R1 (with the BIAS pin pulled to V+). The gains for Table 2. Gain of 7 Filter Configurations GAIN V/V 7.0 7.0 7.0 7.0 dB 16.902 16.902 16.902 16.902 fO (MHz) 10.38 9.57 8.96 8.12 f-3dB (MHz) 7.43 10.36 12.10 7.49 Q 0.539 0.771 1.175 0.656 R1 () 57.14 57.14 57.14 57.14 R2 () 400.00 400.00 400.00 400.00 C1 (pF) 48.2 48.2 48.2 58.75 C2 (pF) 97.6 114.8 130.9 130.9 ein (nV/Hz) 6.1 6.1 6.1 6.1 these topologies range from 1V/V to 7V/V. The Qs listed are within the range of 0.54 and 1.72. The fOs listed are in the range of 6.96MHz and 22.71MHz, and the -3dB frequencies listed range from 5.5MHz to 27.5MHz. For all filters listed, R3 = 125. Figures 7 to 10 show how to pin-strap each filter configuration. Table 3. Gain of 6 Filter Configurations GAIN V/V 6.0 6.0 6.0 6.0 6.0 dB 15.563 15.563 15.563 15.563 15.563 fO (MHz) 10.38 9.57 8.67 8.12 7.47 f-3dB (MHz) 10.03 12.52 7.67 9.59 6.07 Q 0.684 1.071 0.634 0.870 0.592 R1 () 66.67 66.67 66.67 66.67 66.67 R2 () 400.00 400.00 400.00 400.00 400.00 C1 (pF) 48.2 48.2 58.75 58.75 69.3 C2 (pF) 97.6 114.8 114.8 130.9 130.9 ein (nV/Hz) 6.2 6.2 6.2 6.2 6.2 Table 4. Gain of 5 Filter Configurations GAIN V/V 5.0 5.0 5.0 5.0 5.0 5.0 5.0 5.0 dB 13.979 13.979 13.979 13.979 13.979 13.979 13.979 13.979 fo (MHz) 11.36 10.38 9.40 8.67 8.12 7.98 7.47 6.96 f-3dB (MHz) 9.67 12.78 7.67 10.07 11.25 6.46 8.16 5.50 Q 0.614 0.936 0.594 0.849 1.290 0.591 0.779 0.579 R1 () 80.00 80.00 80.00 80.00 80.00 80.00 80.00 80.00 R2 () 400.00 400.00 400.00 400.00 400.00 400.00 400.00 400.00 C1 (pF) 48.2 48.2 58.75 58.75 58.75 69.3 69.3 79.85 C2 (pF) 81.5 97.6 97.6 114.8 130.9 114.8 130.9 130.9 ein nV/Hz 6.5 6.5 6.5 6.5 6.5 6.5 6.5 6.5 66012f 22 LTC6601-2 APPLICATIONS INFORMATION Table 5. Gain of 4 Filter Configurations GAIN V/V 4.0 4.0 4.0 4.0 4.0 4.0 4.0 4.0 4.0 dB 12.041 12.041 12.041 12.041 12.041 12.041 12.041 12.041 12.041 fO (MHz) 11.36 10.38 9.40 8.67 8.65 7.98 7.43 7.47 6.96 f-3dB MHz 13.05 14.80 10.47 12.00 6.76 8.84 6.09 10.00 7.57 Q 0.834 1.480 0.799 1.284 0.575 0.794 0.596 1.141 0.775 R1 () 100.00 100.00 100.00 100.00 100.00 100.00 100.00 100.00 100.00 R2 () 400.00 400.00 400.00 400.00 400.00 400.00 400.00 400.00 400.00 C1 (pF) 48.2 48.2 58.75 58.75 69.3 69.3 79.85 69.3 79.85 C2 (pF) 81.5 97.6 97.6 114.8 97.6 114.8 114.8 130.9 130.9 ein nV/Hz 6.8 6.8 6.8 6.8 6.8 6.8 6.8 6.8 6.8 Table 6. Gain of 3 Filter Configurations GAIN V/V 3.0 3.0 3.0 3.0 3.0 3.0 3.0 3.0 3.0 3.0 3.0 3.0 3.0 3.0 3.0 3.0 3.0 dB 9.542 9.542 9.542 9.542 9.542 9.542 9.542 9.542 9.542 9.542 9.542 9.542 9.542 9.542 9.542 9.542 9.542 fO (MHz) 16.06 14.68 13.53 13.29 12.26 11.36 11.48 11.29 10.29 10.57 9.40 8.65 8.06 7.98 7.43 6.96 9.85 f-3dB (MHz) 12.36 15.74 17.83 9.88 12.39 15.77 14.07 8.34 11.04 10.06 12.85 9.54 6.69 10.88 8.48 9.40 7.13 Q 0.568 0.763 1.091 0.554 0.715 1.300 0.928 0.552 0.763 0.674 1.224 0.788 0.601 1.212 0.825 1.172 0.544 R1 () 66.67 66.67 66.67 66.67 66.67 133.33 66.67 66.67 133.33 66.67 133.33 133.33 133.33 133.33 133.33 133.33 66.67 R2 () 200.00 200.00 200.00 200.00 200.00 400.00 200.00 200.00 400.00 200.00 400.00 400.00 400.00 400.00 400.00 400.00 200.00 C1 (pF) 48.2 48.2 48.2 58.75 58.75 48.2 58.75 69.3 58.75 69.3 58.75 69.3 79.85 69.3 79.85 79.85 79.85 C2 (pF) 81.5 97.6 114.8 97.6 114.8 81.5 130.9 114.8 81.5 130.9 97.6 97.6 97.6 114.8 114.8 130.9 130.9 ein (nV/Hz) 7.1 7.1 7.1 7.1 7.1 7.4 7.1 7.1 7.4 7.1 7.4 7.4 7.4 7.4 7.4 7.4 7.1 66012f 23 LTC6601-2 APPLICATIONS INFORMATION Table 7. Gain of 2 Filter Configurations GAIN V/V 2.0 2.0 2.0 2.0 2.0 2.0 2.0 2.0 2.0 2.0 2.0 2.0 2.0 2.0 2.0 2.0 dB 6.021 6.021 6.021 6.021 6.021 6.021 6.021 6.021 6.021 6.021 6.021 6.021 6.021 6.021 6.021 6.021 fO (MHz) 16.06 14.55 14.68 13.29 12.24 12.26 11.29 10.29 10.51 10.57 9.47 9.85 8.82 8.65 8.06 7.43 f-3dB (MHz) 18.95 12.69 20.46 15.34 10.96 16.66 12.98 13.97 9.76 13.97 10.52 11.17 7.55 11.91 9.48 10.40 Q 0.868 0.626 1.323 0.840 0.640 1.200 0.835 1.197 0.660 1.102 0.796 0.819 0.616 1.254 0.864 1.341 R1 () 100.00 100.00 100.00 100.00 100.00 100.00 100.00 200.00 100.00 100.00 200.00 100.00 200.00 200.00 200.00 200.00 R2 () 200.00 200.00 200.00 200.00 200.00 200.00 200.00 400.00 200.00 200.00 400.00 200.00 400.00 400.00 400.00 400.00 C1 (pF) 48.2 58.75 48.2 58.75 69.3 58.75 69.3 58.75 79.85 69.3 69.3 79.85 79.85 69.3 79.85 79.85 C2 (pF) 81.5 81.5 97.6 97.6 97.6 114.8 114.8 81.5 114.8 130.9 81.5 130.9 81.5 97.6 97.6 114.8 ein (nV/Hz) 8.1 8.1 8.1 8.1 8.1 8.1 8.1 8.5 8.1 8.1 8.5 8.1 8.5 8.5 8.5 8.5 Table 8. Gain of 1.667 Filter Configurations GAIN V/V 1.667 1.667 1.667 1.667 1.667 1.667 1.667 1.667 1.667 dB 4.437 4.437 4.437 4.437 4.437 4.437 4.437 4.437 4.437 fO (MHz) 19.67 17.97 16.57 16.28 15.01 14.33 13.82 12.94 12.06 f-3dB MHz 19.35 22.12 23.16 15.60 17.80 18.58 13.19 14.77 11.32 Q 0.696 0.934 1.336 0.679 0.875 1.046 0.676 0.826 0.666 R1 () 80.00 80.00 80.00 80.00 80.00 80.00 80.00 80.00 80.00 R2 () 133.33 133.33 133.33 133.33 133.33 133.33 133.33 133.33 133.33 C1 (pF) 48.2 48.2 48.2 58.75 58.75 58.75 69.3 69.3 79.85 C2 (pF) 81.5 97.6 114.8 97.6 114.8 126 114.8 130.9 130.9 ein nV/Hz 8.5 8.5 8.5 8.5 8.5 8.5 8.5 8.5 8.5 66012f 24 LTC6601-2 APPLICATIONS INFORMATION Table 9. Gain of 1.333 Filter Configurations GAIN V/V 1.333 1.333 1.333 1.333 1.333 1.333 1.333 1.333 1.333 1.333 1.333 dB 2.499 2.499 2.499 2.499 2.499 2.499 2.499 2.499 2.499 2.499 2.499 fO (MHz) 19.67 17.82 17.97 16.28 14.99 15.01 14.06 13.82 12.88 12.94 12.06 f-3dB MHz 22.73 15.77 24.34 18.44 13.58 19.82 20.12 15.61 12.03 16.64 13.45 Q 0.841 0.633 1.185 0.818 0.646 1.097 1.506 0.814 0.663 1.025 0.801 R1 () 100.00 100.00 100.00 100.00 100.00 100.00 100.00 100.00 100.00 100.00 100.00 R2 () 133.33 133.33 133.33 133.33 133.33 133.33 133.33 133.33 133.33 133.33 133.33 C1 (pF) 48.2 58.75 48.2 58.75 69.3 58.75 58.75 69.3 79.85 69.3 79.85 C2 (pF) 81.5 81.5 97.6 97.6 97.6 114.8 130.9 114.8 114.8 130.9 130.9 ein nV/Hz 9.4 9.4 9.4 9.4 9.4 9.4 9.4 9.4 9.4 9.4 9.4 Table 10. Gain of 1 Filter Configurations GAIN V/V 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 dB 0.0 0.0 0.0 0.0 0.0 0.0 0.0 0.0 0.0 0.0 0.0 0.0 0.0 0.0 0.0 0.0 0.0 0.0 0.0 0.0 0.0 0.0 fO (MHz) 22.71 20.75 20.57 19.14 18.80 17.31 17.33 16.23 15.96 14.55 14.87 14.95 13.39 13.92 12.48 12.24 11.40 11.29 10.51 9.47 8.82 8.06 f-3dB MHz 25.40 27.23 17.86 27.50 20.62 15.35 22.15 22.58 17.45 19.09 13.57 18.59 14.90 15.04 11.38 16.25 13.27 16.47 14.17 13.26 10.86 11.57 Q 0.804 1.079 0.623 1.543 0.784 0.634 1.011 1.312 0.781 1.079 0.650 0.954 0.798 0.769 0.650 1.115 0.850 1.715 1.167 1.350 0.935 1.535 R1 () 100.0 100.0 100.0 100.0 100.0 100.0 100.0 100.0 100.0 200.0 100.0 100.0 200.0 100.0 200.0 200.0 200.0 200.0 200.0 400.0 400.0 400.0 R2 () 100.0 100.0 100.0 100.0 100.0 100.0 100.0 100.0 100.0 200.0 100.0 100.0 200.0 100.0 200.0 200.0 200.0 200.0 200.0 400.0 400.0 400.0 C1 (pF) 48.2 48.2 58.75 48.2 58.75 69.3 58.75 58.75 69.3 58.75 79.85 69.3 69.3 79.85 79.85 69.3 79.85 69.3 79.85 69.3 79.85 79.85 C2 (pF) 81.5 97.6 81.5 114.8 97.6 97.6 114.8 130.9 114.8 81.5 114.8 130.9 81.5 130.9 81.5 97.6 97.6 114.8 114.8 81.5 81.5 97.6 ein nV/Hz 10.7 10.7 10.7 10.7 10.7 10.7 10.7 10.7 10.7 11 10.7 10.7 11 10.7 11 11 11 11 11 11.8 11.8 11.8 66012f 25 LTC6601-2 APPLICATIONS INFORMATION 20 1 2 4 5 19 18 17 16 15 1 2 4 5 20 19 18 17 16 15 LTC6601-2 LTC6601-2 + R1 66.66 + - 11 R1 57.14 - 11 6 7 8 9 10 6 7 8 9 10 20 1 2 4 5 19 18 17 16 15 1 2 4 5 20 19 18 17 16 15 LTC6601-2 LTC6601-2 + R1 100 + - 11 R1 80 - 11 6 7 8 9 10 6 7 8 9 10 20 1 2 4 5 19 18 17 16 15 1 2 4 5 20 19 18 17 16 15 LTC6601-2 LTC6601-2 + R1 200 + - 11 R1 133.33 - 11 6 7 8 9 10 6 7 8 9 10 20 1 2 4 5 19 18 17 16 15 LTC6601-2 + - 11 66012 F07 R1 400 6 7 8 9 10 Figure 7. Pin-Strap Hookup for a Particular R1 66012f 26 LTC6601-2 APPLICATIONS INFORMATION 20 1 2 4 5 19 18 17 16 15 1 2 4 5 20 19 18 17 16 15 LTC6601-2 LTC6601-2 + R2 100 + R2 133 - 11 - 11 6 7 8 9 10 6 7 8 9 10 20 1 2 4 5 19 18 17 16 15 1 2 4 5 20 19 18 17 16 15 LTC6601-2 LTC6601-2 + R2 200 + R2 400 - 11 - 11 66012 F08 6 7 8 9 10 6 7 8 9 10 Figure 8. Pin-Strap Hookup for a Particular R2 20 1 2 4 5 19 18 17 16 15 1 2 4 5 20 19 18 17 16 15 LTC6601-2 LTC6601-2 + C1 48.2pF + C1 58.75pF - 11 - 11 6 7 8 9 10 6 7 8 9 10 20 1 2 4 5 19 18 17 16 15 1 2 4 5 20 19 18 17 16 15 LTC6601-2 LTC6601-2 + C1 69.3pF + C1 79.85pF - 11 - 11 6 7 8 9 10 6 7 8 9 10 66012 F09 Figure 9. Pin-Strap Hookup for a Particular C1 66012f 27 LTC6601-2 APPLICATIONS INFORMATION 20 1 2 4 5 19 18 17 16 15 1 2 4 5 20 19 18 17 16 15 LTC6601-2 LTC6601-2 + C2 81.5pF + C2 114.8pF - 11 - 11 6 7 8 9 10 6 7 8 9 10 20 1 2 4 5 19 18 17 16 15 1 2 4 5 20 19 18 17 16 15 LTC6601-2 LTC6601-2 + C2 97.6pF + C2 130.9pF - 11 - 11 6 7 8 9 10 6 7 8 9 10 66012 F10 Figure 10. Pin-Strap Hookup for a Particular C2 66012f 28 LTC6601-2 APPLICATIONS INFORMATION Example Filter Configurations of Basic 2nd Order Filters Figure 11 shows some simplified component hookups of a selection of filters taken from Tables 7, 9 and 10. For simplicity, VOCM pin bypass and power supply bypass are not shown. 20 1 2 VIN 4 5 19 18 17 16 15 1 2 VOUT(DIFF) VIN 4 11 5 20 19 18 17 16 15 LTC6601-2 LTC6601-2 + - + VOUT(DIFF) - 11 6 7 8 9 10 6 7 8 9 10 GAIN = 0dB fO = 13.92MHz Q = 0.769 GAIN = 0dB fO = 22.71MHz Q = 0.804 20 1 2 VIN 4 5 19 18 17 16 15 1 2 VOUT(DIFF) VIN 4 11 5 20 19 18 17 16 15 LTC6601-2 LTC6601-2 + - + VOUT(DIFF) - 11 6 7 8 9 10 6 7 8 9 10 GAIN = 6dB fO = 9.85MHz Q = 0.819 GAIN = 6dB fO = 16.06MHz Q = 0.868 20 1 2 VIN 4 5 19 18 17 16 15 1 2 VOUT(DIFF) VIN 4 11 5 20 19 18 17 16 15 LTC6601-2 LTC6601-2 + - + VOUT(DIFF) - 11 6 7 8 9 10 6 7 8 9 10 66012 F11 GAIN = 2.5dB fO = 12.06MHz Q = 0.801 GAIN = 2.5dB fO = 19.67MHz Q = 0.841 Figure 11. Basic 2nd Order Filter Configurations 66012f 29 LTC6601-2 APPLICATIONS INFORMATION Figure 12 shows some simplified component hookups of a selection of filters taken from Tables 4, 5, and 6. For 20 1 2 VIN 4 5 19 18 17 16 15 1 2 VOUT(DIFF) VIN 4 11 5 simplicity, VOCM pin bypass and power supply bypass are not shown. 20 19 18 17 16 15 LTC6601-2 LTC6601-2 + - + VOUT(DIFF) - 11 6 7 8 9 10 6 7 8 9 10 GAIN = 12dB fO = 6.96MHz Q = 0.775 GAIN = 12dB fO = 11.36MHz Q = 0.834 20 1 2 VIN 4 5 19 18 17 16 15 1 2 VOUT(DIFF) VIN 4 11 5 20 19 18 17 16 15 LTC6601-2 LTC6601-2 + - + VOUT(DIFF) - 11 6 7 8 9 10 6 7 8 9 10 GAIN = 14dB fO = 6.96MHz Q = 0.579 GAIN = 14dB fO = 11.36MHz Q = 0.614 20 1 2 VIN 4 5 19 18 17 16 15 1 2 VOUT(DIFF) VIN 4 11 5 20 19 18 17 16 15 LTC6601-2 LTC6601-2 + - + VOUT(DIFF) - 11 6 7 8 9 10 6 7 8 9 10 66012 F12 GAIN = 9.54dB fO = 9.85MHz Q = 0.544 GAIN = 9.54dB fO = 16.06MHz Q = 0.568 Figure 12. Basic 2nd Order Filter Configurations 66012f 30 LTC6601-2 APPLICATIONS INFORMATION COMPLEX FILTER CONFIGURATIONS A Modified 2nd Order Lowpass Filter Topology The basic filter topology of Figure 3 can be modified as shown in Figure 13. The Figure 13 circuit includes an impedance path between the two summing nodes (the circuit nodes common to resistors R1, R2 and R3). A resistor and/or a capacitor connection between the summing nodes provide even more flexibility, and enhance the filter design options (the fO and Q equations shown in Figure 13 reduce to equations of Figure 3 if C3 is zero and R4 is infinite). The modified second order filter topology provides for setting the Q value (with R4) without changing the fO value and increasing the passband gain to greater than one without changing the Q value (in the Q equation of Figure 13 the value of Q does not change if the value of the [1 + GAIN + 2(R2/R4)] denominator factor does not change). Using R4 to set the Q value allows the option to design the -3dB frequency (f3dB). If the Q value varies and the fO value is constant then the f3dB frequency varies in a second order lowpass function (refer to the f3dB equation of Figure 13). Figures 14 to 17 show additional circuits highlighting the use of R4 or C3 in the modified second order cicuit to set the f3dB frequency to 13MHz, 19MHz, 22.7MHz and 24.6MHz respectively. The design procedure for a specified f3dB frequency is as follows: 1 Using the chosen C1, C2 and C3 values calculate the fO value. 2. Using fO of step 1 and the specified f3dB calculate the Q value. 3. Calculate the R4 value using the Q value of step 3. 4. Calculate the required external resistor REXT value for the R4 value in step 3. Example, in Figure 14 the Q value for f3dB = 5MHz is 0.54, the required R4 resistor is 350, the R4A and R4B resistors are the internal 100 and the REXT resistor is 150 [REXT = R4 - (R4A + R4B)]. Note: The modified second order filter topology requires the use of at least two of the three input resistor pairs (two of the three 400, 200 and 100 pairs). 66012f 31 LTC6601-2 APPLICATIONS INFORMATION R2 C2 R1 R4A C3A VIN(DIFF) REXT R4B R1 49.9 C3B R3 C1 +- VOUT(DIFF) -+ R3 C1 C2 R2 66012 F13 R4 = R4A + R4B + REXT C3 = C3A /2 (C3A = C3B) fO * f3dB = 6089 * (3568 * Q 4 1788 * Q 2 + 447 + 1.287 * 105 * 2 * Q 2 507.6 * Q ) ( 1 ) ( 0.2236 * fO * Q= 2.109 * 105 * (9.891* 10 * f (16 * f * (8.29 * 10 * f 12 O 2 9 3dB 4 5.486 * 109 * fO4 + 120 * 5.526 * 109 * f3dB2 + 3.082 * 106 * fO2 2 ) 3dB + 4.127 * 109 * fO2 ) 6.638 * 1010 * f3dB 4 ) ) R4 = 559 * C1* R2 * 1.25 * 10 4 * C1* Q * R2 C2 + 2 * C3 C1 50 * Q * C1* (125 * GAIN + R2 + 125) C2 * R2 ( ) VOUT(DIFF) VIN(DIFF) =- S2 + VOUT(DIFF) VIN(DIFF) R1* R2 * (2 * R3 + R4) + R3 * R4 + R2 * R3 * R4 R1* R2 * R3 * R4 * (C2 + 2 * C3) ( GAIN R2 * R3 * C1* (C2 + 2 * C3) ) *S+ 1 R2 * R3 * C1* (C2 + 2 * C3) GAIN = - =- R2 R1 R3 * R2 C2 C3 +2* C1 C1 R2 R3 C2 - * R4 R2 C1 fO = 2* * R2 * R3 * C1* (C2 + 2 * C3) 1 Q= 1+ 1+| GAIN | + 2 * Figure 13. Modified Filter Topology and Equations 66012f 32 LTC6601-2 APPLICATIONS INFORMATION 20 1 2 200 4 5 19 18 17 16 15 1 2 4 5 20 19 18 17 16 15 LTC6601-2 LTC6601-2 + VOUT(DIFF) VIN(DIFF) ZIN(DIFF) = 200 + VOUT(DIFF) VIN(DIFF) ZIN(DIFF) = 400 - 11 - 11 6 7 8 9 10 6 7 8 9 10 GAIN = 1 fO = 11.28MHz Q = 0.835 f-1dB = 10MHz f-3dB = 13MHz GAIN = 2 fO = 11.28MHz Q = 0.835 f-1dB = 10MHz f-3dB = 13MHz 66012 F14a Gain Magnitude vs Frequency (Gain = 1) 5 0 -5 PHASE (DEG) -10 GAIN (dB) -15 -20 -25 -30 -35 -40 100k 1M 10M FREQUENCY (Hz) 100M 66012 F14b Passband Phase and Group Delay 30 0 -30 -60 -90 -120 50 40 GROUP DELAY 30 20 10 0 100k 4M 8M 12M FREQUENCY (Hz) 0 16M 66012 F14c PHASE GROUP DELAY (ns) Figure 14. Modified Filter Configuration Using a Resistor Between Summing Nodes (f-3dB = 13MHz) 66012f 33 LTC6601-2 APPLICATIONS INFORMATION 20 1 2 200 4 5 19 18 17 16 15 1 VIN(DIFF) ZIN(DIFF) = 200 2 4 11 5 20 19 18 17 16 15 LTC6601-2 LTC6601-2 + VOUT(DIFF) + VOUT(DIFF) VIN(DIFF) ZIN(DIFF) = 400 - - 11 6 7 8 9 10 6 7 8 9 10 66012 F15a GAIN = 1 fO = 16MHz Q = 0.868 f-1dB = 15.4MHz f-3dB = 19MHz GAIN = 2 fO = 16MHz Q = 0.868 f-1dB = 15.4MHz f-3dB = 19MHz Gain Magnitude vs Frequency (Gain = 1) 5 0 -5 PHASE (DEG) -10 GAIN (dB) -15 -20 -25 -30 -35 -40 100k 1M 10M FREQUENCY (Hz) 100M 66012 F15b Passband Phase and Group Delay 30 0 -30 -60 -90 -120 50 40 30 GROUP DELAY 20 10 0 100k 4M 8M 12M FREQUENCY (Hz) 16M 0 20M 66012 F15c PHASE GROUP DELAY (ns) Figure 15. Modified Filter Configuration Using a Resistor Between Summing Nodes (f-3dB = 19MHz) 66012f 34 LTC6601-2 APPLICATIONS INFORMATION 20 33.2 1 VIN(DIFF) ZIN(DIFF) = 266 2 4 33.2 5 19 18 17 16 15 1 VIN(DIFF) ZIN(DIFF) = 200 2 4 11 5 20 19 18 17 16 15 LTC6601-2 LTC6601-2 + VOUT(DIFF) + VOUT(DIFF) - - 11 6 7 8 9 10 6 7 8 9 10 GAIN = 1 fO = 19.7MHz Q = 0.84 f-1dB = 19MHz f-3dB = 22.7MHz GAIN = 1.33 fO = 19.7MHz Q = 0.84 f-1dB = 19MHz f-3dB = 22.7MHz 66012 F16a Gain Magnitude vs Frequency (Gain = 1) 5 0 -5 PHASE (DEG) -10 GAIN (dB) -15 -20 -25 -30 -35 -40 100k 1M 10M FREQUENCY (Hz) 100M 66012 F16b Passband Phase and Group Delay 30 0 -30 -60 -90 -120 50 40 30 GROUP DELAY 0 100k 20 10 4.6M 9.2M 13.8M 18.4M FREQUENCY (Hz) 0 23M GROUP DELAY (ns) PHASE 66012 F16c Figure 16. Modified Filter Configuration Using a Resistor Between Summing Nodes (f-3dB = 22.7MHz) 66012f 35 LTC6601-2 APPLICATIONS INFORMATION Passband Gain vs Frequency 20 1 VIN(DIFF) ZIN(DIFF) = 200 2 49.9 4 5 19 18 17 16 15 1.0 0.5 0.0 GAIN (dB) -0.5 -1.0 -1.5 -2.0 6 7 8 9 10 -2.5 -3.0 100k 1M 10M FREQUENCY (Hz) 40M 66012 F17b LTC6601-2 + VOUT(DIFF) - 11 GAIN = 1 fO = 20.7MHz Q = 0.88 f-1dB = 20.5MHz f-3dB = 24.6MHz 66012 F17a Gain Magnitude vs Frequency (Gain = 1) 5 0 -5 PHASE (DEG) GAIN (dB) -10 -15 -20 -25 -30 -35 100k 1M 10M FREQUENCY (Hz) 100M 66012 F17c Passband Phase and Group Delay 30 0 -30 -60 -90 -120 50 40 30 GROUP DELAY 0 100k 20 10 5.2M 10.4M 15.6M 20.8M FREQUENCY (Hz) 0 26M GROUP DELAY (ns) PHASE 66012 F17d Figure 17. Modified Filter Configuration Using a Capacitor Between Summing Nodes (f-3dB = 24.6MHz) 66012f 36 LTC6601-2 APPLICATIONS INFORMATION DC1251A Demonstration Board The DC1251A demonstration circuit contains an LTC6601-2 (DC1251A-B). On a DC1251A the LTC6601 programming pins can be connected through 0603 resistor jumpers. In addition, optional surface mount capacitors and inductors at the LTC6601 input and/or output can be installed for additional filtering (a lowpass filter up to a 5th order can be implemented with a DC1251A demonstration circuit). The DC1251A has SMA connectors for the differential input and output of the LTC6601. An on board 106MHz lowpass RC filters the LTC6601 output. DC1251A Top Silk Screen 66012f 37 LTC6601-2 38 LTC6601-X Demonstration Circuit DC1251A RF2 RG1 20 RG2 IN3+ 1 IN2+ OUT V+ LTC6601-2 V- VOCM OUT C1 7 C2 8 C3 9 C4 10 11 R2 49.9, 1% 12 13 C10 0.01F C11 1000pF 14 C9 10pF IN1+ BIAS IN1- IN2- IN- 6 R4 20 1% (OPT) V R5 20 1% (OPT) RF8 RF7 RF9 RF10 + C5 (OPT) 19 C5 15 V+ C6 C7 C8 C8 10pF 18 17 16 R1 49.9, 1% RF1 RF3 RF4 RF5 RF6 J1 VIN+ RG3 2 C2 (OPT) RQ1 4 5 RG5 RG6 RC2 RC3 3 RG4 RIN1 RZ1 J3 VOUT- APPLICATIONS INFORMATION C3 (OPT) C4 (OPT) C1 (OPT) C7 10pF J2 VIN- RIN2 RZ2 J4 VOUT+ C6 (OPT) RF11 RF12 (24AWG-VIA) R3 49.9, 1% C12 0.01F (24AWG-VIA) E3 EXT VOCM E1 V+ IN 2.7V TO 5.5V C14 1F 10V C15 0.1F V+ 1 3 5 JP1 4 6 2 HP LP SHDN C13 10F 10V E2 GND E4 GND (24AQG-VIA) 66012 DC (24AWG-VIA) BOARD ASSEMBLY ASSY DC1251A-A DC1251A-B U1 LTC6601CUF-1#TR LTC6601CUF-2#TR 66012f LTC6601-2 PACKAGE DESCRIPTION UF Package 20-Lead Plastic QFN (4mm x 4mm) (Reference LTC DWG # 05-08-1710) 0.70 0.05 4.50 0.05 3.10 0.05 2.45 0.05 (4 SIDES) PACKAGE OUTLINE 0.25 0.05 0.50 BSC RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS BOTTOM VIEW--EXPOSED PAD 4.00 0.10 (4 SIDES) PIN 1 TOP MARK (NOTE 6) 0.75 0.05 R = 0.115 TYP PIN 1 NOTCH R = 0.30 TYP 19 20 0.38 1 2 0.10 2.45 0.10 (4-SIDES) (UF20) QFN 10-04 0.200 REF 0.00 - 0.05 NOTE: 1. DRAWING IS PROPOSED TO BE MADE A JEDEC PACKAGE OUTLINE MO-220 VARIATION (WGGD-1)--TO BE APPROVED 2. DRAWING NOT TO SCALE 3. ALL DIMENSIONS ARE IN MILLIMETERS 4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE 5. EXPOSED PAD SHALL BE SOLDER PLATED 6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE 0.25 0.05 0.50 BSC 66012f Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights. 39 LTC6601-2 TYPICAL APPLICATION 5th Order, 20MHz, Lowpass Filter 20 33.2 220nH* VIN(DIFF) ZIN(DIFF) = 266 33.2 82pF 82pF 82pF 220nH* 5 *COILCRAFT 0603CS 6 7 8 9 10 270pF 4 2 1 19 18 17 16 15 LTC6601-2 + VOUT(DIFF) - 11 66012 TA02a Gain Magnitude vs Frequency 10 0 -10 GAIN (dB) GAIN (dB) -20 -30 -40 -50 -60 -70 100k 1M 10M FREQUENCY (Hz) 100M 66012 TA02b Passband Gain vs Frequency 1.0 0.5 0 -0.5 -1.0 -1.5 -2.0 -2.5 -3.0 100k 1M FREQUENCY (Hz) 10M 66012 TA02c RELATED PARTS PART NUMBER LT(R)1568 LT1993-2/LT1993-4/ LT1993-10 LT1994 LT6402-6/LT6402-12/ LT6402-20 LTC6404-1 LTC6404-2 LTC6404-4 LT6600-2.5/LT6600-5/ LT6600-10/LT6600-20 LTC6601-1 LTC6602 LTC6603 LT6604-X LTC6605-X DESCRIPTION Very Low Noise, High Frequency, Active RC, Filter Building Block 800MHz/900MHz/700MHz Low Distortion, Low Noise Differential Amplifier/ADC Driver Low Noise, Low Distortion Fully differential Input/Output Amplifier/Driver 300MHz Low Distortion, Low Noise Differential Amplifier/ ADC Driver Fully Differential Amplifier, GBW = 500MHz Fully Differential Amplifier, GBW = 900MHz Fully Differential Amplifier, GBW = 1700MHz Very Low Noise, Fully Differential Amplifier and Filter Low Noise, Pin-Configurable Filter Dual, Matched Bandpass Filter Dual, Matched Lowpass Filter Dual, Matched Lowpass Filter Dual, Matched Lowpass Filter COMMENTS Up to 10MHz Filters, SNR = 92dB, THD = -84dBc at 2MHz AV = 2V/V / AV = 4V/V / AV = 10V/V, NF = 12.3dB/14.5dB/12.7dB, OIP3 = 38dBm/40dBm/40dBm at 70MHz Low Distortion, 2VP-P, 1MHz: -94dBc, 13mA, Low Noise: 3nV/Hz AV = 6dB/AV = 12dB/AV = 20dB, NF = 18.6dB/15dB/12.4dB, OIP3 = 49dBm/43dBm/51dBm at 20MHz Very Low Distortion, (2VP-P, 10MHz): -91dBc Very Low Distortion, (2VP-P, 10MHz): -96dBc Very Low Distortion, (2VP-P, 10MHz): -101dBc 2.5MHz/5MHz/10MHz/20MHz Integrated Filter, 3V Supply, SO-8 Package 5MHz to 27MHz Bandwidth, Second Order Differential Filter Programmable Gain and Bandwidth for RFID Applications (40kHz to 1MHz) Programmable Gain and Bandwidth (25kHz to 2.5MHz) 2.5MHz, 5MHz, 10MHz and 15MHz 7MHz, 10MHz and 14MHz 66012f LT 0309 * PRINTED IN USA 40 Linear Technology Corporation (408) 432-1900 1630 McCarthy Blvd., Milpitas, CA 95035-7417 FAX: (408) 434-0507 www.linear.com (c) LINEAR TECHNOLOGY CORPORATION 2009 |
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